The present invention relates to a non-volatile memory, and more particularly, to a method of performing an erase operation on a non-volatile memory cell with an oxide-nitride-oxide (ONO) structure.
Non-volatile memory devices have been developed by the semiconductor integrated circuit industry for various applications such as computers and digital communications. A variety of non-volatile memory devices with oxide-nitride-oxide (ONO) structures have been developed. An example of a typical non-volatile memory cell with an ONO structure includes a semiconductor substrate with source and drain regions, an oxide-nitride-oxide (ONO) film on top of the substrate surface between the source and the drain, a nitride layer on top of the first oxide layer, and a second oxide layer on top of the nitride layer. The nitride layer of the ONO film is capable of trapping electrons which are generated in the channel region of the semiconductor substrate during a programming operation.
The conventional non-volatile memory cell with a typical ONO structure is programmed by generating hot electrons in the vicinity of the drain region in the substrate and injecting the hot electrons into the ONO film. The hot electrons are trapped in a portion of the nitride layer close to the drain of the non-volatile memory cell. Because the nitride layer is an insulator, the hot electrons tend to remain in the portion of the nitride layer close to the drain without dispersing into other portions such as the center of the nitride layer.
The presence of negative charge in the portion of the nitride layer adjacent the drain indicates that at least the drain side of the non-volatile memory cell is in a xe2x80x9cprogrammedxe2x80x9d state. The non-volatile memory cell with a typical ONO structure may be programmed by applying high positive voltages to the gate and the drain, and grounding the source to inject hot electrons into the portion of the nitride layer adjacent the drain. An example of typical gate and drain voltages applied during programming are VG=9.0V and VD=4.0V. The program technique described is called channel hot electron programming.
A programming procedure may also be applied to inject hot electrons into the nitride layer of a cell close to the source. To provide electrons in the nitride layer near the source, a positive gate and source voltage are applied while the drain is grounded.
FIG. 1 shows a cross-sectional view of a non-volatile volatile memory cell 2 which comprises a substrate 4, an oxide-nitride-oxide (ONO) film 6 including a first oxide layer 8 on top of the substrate 4, a nitride layer 10 of top of the first oxide layer 8, and a second oxide layer 12 on top of the nitride layer 10. A polysilicon gate 14 is provided on top of the second outside layer 12. Portions of the substrate 4 are doped with a group V element, such as arsenic, to form a source region 16 and a drain region 18. The source and drain regions 16 and 18 may be produced by implanting arsenic into the substrate 4 to a depth in the range of about 300 xc3x85 to about 600 xc3x85. The ONO film 6 is positioned on top of a surface of the substrate 4 between the source 16 and the drain 18.
The first oxide layer 8, which is also called a tunnel oxide layer, is positioned directly on top of the surface portion 20 of the substrate 4 between the source 16 and the drain 18. A channel exists in the substrate 4 beneath the first oxide layer 8 between the source 16 and drain 18. The first oxide layer 8 may have a thickness on the order of about 75 xc3x85.
The nitride layer 10, which is positioned on top of the first nitride layer 8, is capable of trapping hot electrons which are generated in the channel and injected into a portion 34 of the nitride layer 10 close to the drain region 18 during a typical programming operation. The nitride layer 10 may have a thickness on the order of about 75 xc3x85. The second oxide layer 12, which is positioned on top of the nitride layer 10, has a thickness typically on the order of about 100 xc3x85. The gate 14, which is positioned on top of the second oxide layer 12, may be a conventional polysilicon gate which serves as a control gate for the non-volatile memory cell. The ONO film 6, which includes the first oxide layer 8, the second oxide layer 12 and the nitride layer 10 sandwiched between the first and second oxide layers 8 and 12, may be fabricated by using conventional techniques known to a person skilled in the art.
FIG. 1 further shows portions of cross-sectional views of additional memory cells 22 and 24 adjacent the memory cell 2 in a non-volatile memory array. The non-volatile memory cells 22 and 24 each have a device structure identical to the non-volatile memory cell 2 described above. Furthermore, two adjacent non-volatile memory cells share a common arsenic-doped region which serves both as the drain for one of the cells and as the source for the other cell. For example, the arsenic-doped region 16, which serves as the source for the non-volatile memory cell 2, also serves as the drain for the non-volatile memory cell 22. Similarly, the arsenic-doped region 18, which serves as the drain for the non-volatile memory cell 2, also serves as the source for the non-volatile memory cell 24. The drain regions 16 and 18 are buried beneath oxide regions 15 and 17 used to isolate individual cells.
FIG. 2 shows a typical electron charge distribution in the substrate 4 after a typical programming operation in which channel hot electrons are generated in the substrate 4 and then trapped in the nitride layer 10 near the drain 18. When the non-volatile memory cell 2 is programmed by applying a high gate and drain voltage while grounding the source, negative charge 32 is stored in the nitride layer 10 and is localized in the area 34 near the drain 18. The hot electrons are trapped in the localized area 34 of the nitride layer 10 and remain localized without spreading or dispersing into other regions since the nitride layer 10 is an insulator.
FIG. 3 illustrates the distribution of electrons when the non-volatile memory cell 2 is programmed by applying a high source and gate voltage while grounding the drain. As shown, by programming with a high source voltage, negative charge 32 is stored in the nitride layer 10 and is localized in the area 36 near the source. The hot electrons are trapped in the localized area 36 and remain localized without spreading or dispersing.
A single cell can be programmed using the programming procedure where a high drain and gate voltage is applied while the source is grounded, as well as the procedure where a high source and gate voltage is applied while the drain is ground. After both procedures are applied, electrons will be distributed in the nitride layer 10 in both localized regions 34 and 36, as shown in FIG. 4. As further illustrated in FIG. 4, the center of the nitride layer 10 tends to be free of electrons, and the electron distribution does not significantly disperse.
To read the programmed state of the cell programmed, as shown in FIG. 2, in a first (normal) procedure, a positive gate voltage is applied along with a positive source voltage while the drain is grounded. With the cell programmed, a greater threshold voltage V will be created, so a greater gate to source voltage must be applied for the cell to conduct during read. With a higher threshold voltage, for the same read voltage applied, less source to drain current will flow.
A second (complementary) read procedure can be applied with the cell programmed as shown in FIG. 2 which uses a positive gate voltage applied along with a positive drain voltage and the source grounded. With the electrons stored near the drain in region 34, using the complementary read procedure the cell will not significantly change in threshold, unlike when the normal procedure is applied. Thus, using the complementary read procedure, the cell will appear to be unprogrammed whether or not electrons are stored in the region 34.
FIGS. 5A and 5B illustrate both the normal and complementary read procedures applied when a cell has been programmed to store electrons only in the area 34 as shown in FIG. 2. As shown in FIG. 5A, in the normal read procedure a gate voltage of 4.0 volts is applied with a source voltage of 1.4 volts and the drain grounded. With the normal read procedure, as the program time is increased to increase the number of electrons stored in the area 34 of the nitride layer 10, the source to drain cell current significantly decreases as shown in FIG. 5A and the cell threshold increases significantly as shown in FIG. 5B. In the complementary read procedure, as shown in FIG. 5B, a gate voltage of 4.0 volts is applied with a drain voltage of 1.4 volts and a source grounded. With the complementary read procedure, as the program time is increased, the source to drain cell current does not significantly change as shown in FIG. 5A, and the threshold also does not significantly indicate any change as shown in FIG. 5B.
The isolation of the electrons in the areas 34 and 36 of the nitride layer 10 during programming enables the cell structure of FIG. 1 to be used to store two bits of information when the cell is programmed as shown in FIG. 4. With the electrons stored in region 34, the normal read procedure described above can be used to determine the state of the first bit stored. With electrons stored in the region 36, the complementary read procedure can be used to read the cell state in a manner similar to the normal read procedure with electrons stored in region 34. The electrons stored in the region 36 will not significantly affect the normal read procedure. With electrons stored in region 36, the complementary read procedure described above can, thus, be used to determine the state of the second bit stored.
In another conventional structure for a non-volatile memory cell shown in FIG. 6, a source 16 and drain 18 are provided in a substrate 4, but the gate structure is somewhat different from the structure shown in FIG. 1. The gate structure shown in FIG. 6 is made up with an oxide layer 40 supporting a polysilicon floating gate 42, instead of the nitride region 10 of FIG. 1, and another oxide region 44 and polysilicon gate region 46 are placed above the polysilicon floating gate 42. With the structure shown in FIG. 6, after programming electrons will be stored in the polysilicon region 42 and will flow evenly throughout the polysilicon, as illustrated, irrespective of whether a high drain voltage or a high source voltage is used during programming.
After the non-volatile memory cell with the ONO structure of FIG. 1 is programmed, it can be erased by using a conventional technique of drain side hot hole injection. In a typical erase procedure for ONO type non-volatile cells, a gate voltage of 0.0 volts is applied along with a large drain voltage on the order of 4.5-6.0 volts while the source is floated or grounded. Alternatively, the gate voltage of 0.0 volts is applied while the source is at 4.5-6.0 volts and the drain is floated or grounded.
FIG. 7 illustrates conditions during an erase procedure for an ONO cell where electrons have been stored only in the area 34. For the erase procedure illustrated it is assumed that a gate voltage of 0.0 volts is applied along with a high drain voltage, while the source is floated. With such erase conditions a to band current is created under the gate. Holes will be generated under these conditions and will accelerate from the n type drain region 18 into the p type substrate 4. The holes generated are accelerated in the electrical field created near the p-n junction at area 44. Some of the accelerated holes will surmount the oxide to silicon interface between the substrate 4 and oxide layer 8 and will be injected into the nitride layer 10. The holes reaching the nitride layer 10 will displace the electrons to effectively erase the cell.
A problem after a number of program and erase procedures is that some electrons can remain in the center portion 46 of the nitride region 10 as illustrated in FIG. 8. This phenomena is known as xe2x80x9cincomplete erasexe2x80x9d. Incomplete erase results because during programming some electrons can be injected into the central region 46 of the nitride 10. Typically during program electrons are mainly injected into the region 34, but it is possible that a hot electron will be injected into the center 46. The concentration of electrons over the nitride region 10 during typical programming where a high gate and drain voltage are applied is illustrated in area 48.
Incomplete erase occurs after a number of programming and erase cycles. With only a limited number of programming steps, the concentration of electrons near the center 46 as shown in FIG. 8 will be typically nonexistent, so the erase procedure will eliminate all electrons from the region 34 of the nitride 10. However, after a number of programming cycles, some electrons will be injected into the region 46. During the erase procedures, holes which are injected into the nitride 10 will have the same distribution as shown in plot 48 as electrons, so some holes can be injected into the central region 46 of the nitride. To assure that incomplete erase does not occur a number of erase procedures can be applied to increase the likelihood that hot holes will go into the region 46 to eliminate all electrons. As the number of program cycles are increased, the number of erase cycles after each programming step to assure incomplete erase does not occur will increase.
FIG. 9 shows a diagram of a number of program-erase (P/E) cycles vs. erase time needed to completely erase a cell for typical program and erase procedure voltages. As shown in FIG. 9, the erase time increases significantly as the number of program-erase cycles increases. The erase time increases rapidly from 1 sec to 1.6 sec or above within the first 2,000 program-erase cycles. Before the number of program-erase cycles reaches 5,500, the erase time for each erase operation may be as much as 1.9 sec. FIG. 9 shows the number of program-erase cycles only up to 5,500. In some practical applications, it is desired that a non-volatile memory cell be subjected to a larger number of program-erase cycles. But, it may be impossible or impractical for the non-volatile memory cell to endure more program-erase cycles without failure.
The non-volatile memory cell structure shown in FIG. 6 does not require increased erase time after a number of program-erase cycles because the electrons will evenly distribute after each program procedure and holes will also evenly distribute after each erase procedure to eliminate any electrons and avoid any incomplete erase. However, the non-volatile cell structure of FIG. 1 may still be desirable over the structure of FIG. 6 for a number of reasons. First, the ONO structure of FIG. 1 enables a 20% reduction in processing costs over the structure of FIG. 6. Further the ONO structure of FIG. 1 is less sensitive to defects. Further, the ONO structure enables two bits per cell to be programmed without increased complexity, as described with respect to FIG. 4 since electrons are concentrated in two discrete areas, as opposed to the even distribution with the structure of FIG. 6.
In accordance with the present invention, an erase procedure includes the step of applying an erase cycle followed by a read cycle until the cell being erased has a threshold reduced below a desired value. For the initial erase cycle, an initial negative gate voltage is applied. In subsequent erase cycles, a sequentially decreasing negative gate voltage is applied until the desired threshold is obtained. A suggested range for the gate erase voltages is less than 0 V to about xe2x88x924 V. An initial gate erase voltage may be on the order of xe2x88x921.0 volts. The negative gate erase voltage applied during the erase operation is continually decreased to reduce erase time required to avoid incomplete erase.
In one embodiment, after erase is complete, the last negative gate voltage value applied is stored in a separate memory. After a subsequent programming when a subsequent erase procedure is again applied, the initial gate voltage value applied during erase is the negative gate voltage value stored in memory. Accordingly, less erase cycles are required to complete the erase procedure. If a lower gate voltage is then needed to complete erase during the subsequent erase procedure, the new lower gate voltage is stored in memory for subsequent erase procedures.
Using a negative gate erase voltage decreases the accumulation of residual charge after each erase operation in comparison to erase with the gate grounded, thereby alleviating the problem of incomplete erase associated with conventional erase operations. Because the residual charge does not accumulate after erase, the threshold voltage VT Of the cell does not shift as drastically after a number of program-erase cycles are applied, eliminating the need to increase erase time. With the negative gate voltage applied during erase, a lower drain voltage is required for the erase procedure than in conventional programming techniques enabling the size of the non-volatile memory cell to be shrunk from cells erased with a conventional procedure.